1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to improvement of a semiconductor memory device having a hierarchical boosted power-line scheme.
2. Description of the Background Art
In recent years, a semiconductor memory device is used in a variety of portable appliances. A battery is generally used as a power source of such a portable appliance. In order to use a portable appliance for a long time with one battery, it is necessary to suppress as much as possible current consumption not only at the time of operation but also at stand-by. Therefore, reduction of power consumption of a semiconductor memory device is very important.
In a dynamic random access memory (DRAM) which is a typical semiconductor memory device, for example, a word line is boosted to a potential higher than a power supply potential Vcc (hereinafter referred to as a "boosted power supply potential Vpp") in order to store an H (logical high) level which is completely equal to the power supply potential Vcc in a memory cell.
FIG. 30 is a block diagram showing an internal boosting circuit and a word line driving circuit (word line driver) used in the DRAM in recent years. Referring to FIG. 30, an internal boosting circuit 20 generates, based on the externally supplied power supply potential Vcc, the boosted power supply potential Vpp higher than the power supply potential Vcc. A word line driver WD is activated/deactivated in response to a decode signal from a decoder unit DU. Word line driver WD is constituted of a CMOS invertor including a P channel MOS transistor Q1 and an N channel MOS transistor Q2. Decoder unit DU and word line driver WD are supplied with the boosted power supply potential Vpp from internal boosting circuit 20.
Word line driver WD in a stand-by state is shown in FIG. 30. In the stand-by state, a decode signal at the H level which is equal to the boosted power supply potential Vpp is supplied to word line driver WD from decoder unit DU, causing P channel MOS transistor Q1 to be turned off and N channel MOS transistor Q2 to be turned on. Therefore, the potential of a word line WL is brought to an L (logical low) level which is equal to a ground potential (0V) by N channel MOS transistor Q2.
On the other hand, when word line driver WD is in an operating state and the word line is selected, a decode signal at the L level is supplied to word line driver WD from decoder unit DU, causing P channel MOS transistor Q1 to be turned on and N channel MOS transistor Q2 to be turned off. Therefore, the boosted power supply potential Vpp is supplied to word line WL through P channel MOS transistor Q1, whereby word line WL is boosted up to the boosted power supply potential Vpp. Since word line driver WD requires a large driving capability in order to drive word line WL, the channel width of P channel MOS transistor Q1 of word line driver WD is set wider than those of the other transistors used in a peripheral circuit.
Generally, although P channel MOS transistor Q1 is in an off state in the stand-by state, a small through current i called a subthreshold current flows from the source to the drain in P channel MOS transistor Q1. The through current i supplied in word line driver WD becomes larger than those in the other transistors used in the peripheral circuit.
Since a 64 M-bit DRAM, for example, includes 32K word lines and 32K word line drivers in total, the sum of the through currents becomes extremely large. As a result, the output potential of internal boosting circuit 20 is decreased from the predetermined boosted power supply potential Vpp. Internal boosting circuit 20 operates in order to bring the decreased output potential back to the original boosted power supply potential. A current flows in from an external power source for this operation of internal boosting circuit 20, thereby increasing current consumption.
A hierarchical boosted power-line scheme in which a plurality of word line drivers are divided into several blocks and the boosted power-lines are made hierarchical in order to reduce such power consumption at stand-by as described above is suggested in "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's," Symposium on VLSI Circuits, Digests of Technical Papers, (1993): 45 and 46. FIG. 31 shows one block of a hierarchical boosted power-line scheme suggested in this article. Referring to FIG. 31, the boosted power supply potential Vpp from internal boosting circuit 20 is directly supplied to a global boosted power-line GPL, and further supplied to a local boosted power-line LPL through a block select transistor BST. By local boosted power-line LPL, n word line drivers WD1 to WDn are connected together. Each of the other blocks (not shown) includes one drive transistor, one local boosted power-line, and n word line drivers, similarly to the block shown in FIG. 31. Therefore, one global boosted power-line GPL shown in FIG. 31 is connected to the local boosted power-line through the drive transistor in each block.
In operation, a block select signal /BS at the L level (in this specification and the drawings, "/" before a signal indicates that the signal is at a negative logical level) is applied to select transistor BST, whereby local boosted power-line LPL is supplied with the boosted power supply potential Vpp. Simultaneously, only one decoder unit selected among n decoder units DU1 to Dun supplies a decode signal at the L level to a corresponding word line driver. Therefore, only one word line driver selected among n word line drivers WD1 to WDn is activated, and the boosted power supply potential Vpp is supplied to a corresponding word line through P channel MOS transistor Q1 in the activated word line driver. Word lines WL1 to WLn have parasitic capacitances C1 to Cn, respectively. As described above, since only one word line driver is activated in one block, it is enough for select transistor BST to have a capability to drive one word line.
On the other hand, at stand-by, all decoder units DU1 to Dun supply decode signals X1 to Xn at the H level to word line drivers WD1 to WDn, respectively. Therefore, all P channel MOS transistors Q1 in word line drivers WD1 to WDn are turned off. Simultaneously, block select signal /BS attains the H level. Therefore, the through currents in these P channel MOS transistors Q1 are limited by select transistor BST, resulting in suppression of the through current at stand-by as a whole.
Although the potential of local boosted power-line LPL is decreased from the boosted power supply potential Vpp, each P channel MOS transistor Q1 is supplied with the boosted power supply potential Vpp at its gate, and therefore, the gate-to-source voltage of P channel MOS transistor Q1 becomes negative. As a result, when the through current flowing in each word line driver reaches 1/n the through current flowing in a drive transistor DT, the potential of local boosted power-line LPL stops decreasing, and is stable at a potential Vpps a little lower than the boosted power supply potential Vpp.
When drive transistor DT is not included and the boosted power supply potential Vpp is always supplied to all the word line drivers, the above through current i flows in each word line driver. On the other hand, in the case of such a hierarchical boosted power-line scheme as described above, only 1/n the through current i flows in each word line driver. Therefore, the sum of the through currents is substantially reduced, which in turn reduces current consumption at stand-by. Further, since a voltage drop (Vpp-Vpps) of local boosted power-line LPL when the semiconductor memory device transitions from the operating state to the stand-by state is small, the potential of local boosted power-line LPL is brought back to the boosted power supply potential Vpp immediately when the semiconductor memory device is again brought to the operating state.
In the above described hierarchical boosted power-line scheme, local boosted power-line LPL is discharged at the time of power on. Local boosted power-line LPL is not charged unless a block including the boosted power-line LPL is selected. Since local boosted power-line LPL starts to be charged when the block is selected, word line drivers WD1 to WDn cannot operate normally unless the local boosted power-line LPL is sufficiently charged up to the boosted power supply potential Vpp. Therefore, it takes time from power on to the start of operation of the DRAM. More specifically, in the hierarchical boosted power-line scheme, an insufficient initial charge of local boosted power-line LPL results in a slow initial access immediately after power on.